1. Field of Invention
The present invention relates to a current mirror, and more particularly, to a chain-chopping current mirror and a method for stabilizing output currents.
2. Description of the Related Art
In various application circuits, such as an amplifier, an multi-channel constant current driver and so on, a current mirror is often required as a bias circuit of the above-mentioned circuits. FIG. 1 is a drawing of a conventional current mirror circuit configuration. Referring to FIG. 1, the current mirror includes five transistors MP1˜MP5. The transistor MP1 produces a bias at the gate thereof according to the input current at an input terminal I101. The gates of the transistors MP2˜MP5 are coupled with the gate of the transistor MP1 to receive the gate bias of the transistor MP1 and the transistors MP2˜MP5 respectively and output a current according to the gate bias and the proportions among the sizes of the transistors MP2˜MP5.
For some applications, the above-mentioned channel sizes of the transistors MP2˜MP5 are equal to each other, which is designed purposely for outputting the same current at every output node (also called ‘current channel’) OUT1˜OUT4. However, due to an imperfect IC (integrated circuit) process, a deviation between the real output current at the output nodes OUT1˜OUT4 and the originally desired current may occurs.
To make the current passing through every current channel equal to each other, a prior art configuration called ‘cross-chopping current mirror’ was provided as shown in FIG. 2. Referring to FIG. 2, in the circuit herein, in addition to the transistors MP1˜MP5 of the original current mirror, two transmission-gates functioning as switches are further disposed between every two adjacent transistors and two adjacent output terminals, i.e. eight transistors in total, SW1˜SW8. By using a first clock signal CK and a second clock signal CKB, the transmission-gates SW1˜SW8 of the circuit are controlled to be turned on or off, wherein the first clock signal CK and the second clock signal CKB are phase-inverted to each other.
When the first clock signal CK takes a logic-high level, the second clock signal CKB takes a logic-low level. At the point, the output node OUT1 outputs a current passing through the transistor MP2, the output node OUT2 outputs a current passing through the transistor MP3, the output node OUT3 outputs a current passing through the transistor MP4 and the output node OUT4 outputs a current passing through the transistor MP5. When the first clock signal CK takes a logic-low level, the second clock signal CKB takes a logic-high level. At the point, the output node OUT1 outputs a current passing through the transistor MP3, the output node OUT2 outputs a current passing through the transistor MP2, the output node OUT3 outputs a current passing through the transistor MP5 and the output node OUT4 outputs a current passing through the transistor MP4.
Although the above-described cross-chopping current mirror is able to average the currents of the current channel OUT1 and the current channel OUT2 and the currents of the current channel OUT3 and the current channel OUT4, respectively, however, output current variations with the above-described design still remain. It is assumed that the desired current of the original design is I; under the process influence, the real output current of the transistor MP2 is I+a, the real output current of the transistor MP3 is I+b, the real output current of the transistor MP4 is I−c and the real output current of the transistor MP5 is I−d; all of a, b, c and a are larger than zero. By using the scheme of the above-described cross-chopping current mirror, the output current at the output nodes OUT1 and OUT2 is I+(a+b)/2, while the output current at the output nodes OUT3 and OUT4 is I−(c+d)/2, therefore, an output current difference between at OUT2 and OUT3 would be (a+b+c+d)/2.